Application of Kalman gain for minimum mean-squared phase-error bound in bang-bang CDRs

Abstract

This thesis presents a phase rotator-based CDR with a Kalman gain estimator which achieve the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. It is hard for a CDR IC to satisfy the jitter tolerance specifications while maintaining low output clock jitter as the data rate increases. It is because the timing requirement tightens with the decreased unit interval whereas the input SNR drops as the front-end bandwidth increases. The jitter tolerance and the recovered clock jitter of a CDR tradeoffs in input SNR-dominated links. Digital domain BB CDRs are being employed in serial links to overcome large process variations. Since the transfer function of a BB phase detector is nonlinear, the selection of design parameters and performance estimation have been performed empirically, based on behavioral time domain simulation results. However, the optimal phase tracking performance of a BB CDR can be estimated by applying the Kalman gain to a linearized BBPD with the Markov chain method. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of the theoretical analysis is supported by behavioral time domain simulation results. The proposed phase rotator-based BB CDR recovers data with a minimum-jitter clock and tracks input accumulation jitter with a Kalman gain-based optimum loop bandwidth estimator which adjust a proportional gain. Fabricated in a 0.11um CMOS process with a 1.2V supply, the BB CDR occupies 0.265 and operates at 10Gb/s with a bit error rate of less than . At a 10Gb/s PRBS, the measured jitter in the recovered clock is 5 , and the power consumption is 82mW, wherein 60mW is consumed in the data recovery.