Clock gating synthesis through reusing existing combinational logic논리 회로의 재활용을 이용한 클락게이팅의 합성
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Shin, Young-Soo | - |
| dc.contributor.advisor | 신영수 | - |
| dc.contributor.author | Han, In-Hak | - |
| dc.contributor.author | 한인학 | - |
| dc.date.accessioned | 2013-09-12T01:55:18Z | - |
| dc.date.available | 2013-09-12T01:55:18Z | - |
| dc.date.issued | 2012 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=486851&flag=dissertation | - |
| dc.identifier.uri | http://hdl.handle.net/10203/180704 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ v, 37 p. ] | - |
| dc.language | eng | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | Clock gating | - |
| dc.subject | gating function | - |
| dc.subject | 클락 게이팅 | - |
| dc.subject | 게이팅 함수 | - |
| dc.subject | factored form | - |
| dc.subject | factored form | - |
| dc.title | Clock gating synthesis through reusing existing combinational logic | - |
| dc.title.alternative | 논리 회로의 재활용을 이용한 클락게이팅의 합성 | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 486851/325007 | - |
| dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
| dc.identifier.uid | 020103677 | - |
| dc.contributor.localauthor | Shin, Young-Soo | - |
| dc.contributor.localauthor | 신영수 | - |
- Appears in Collection
- EE-Theses_Master(석사논문)
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