BER optimal ADC-Equalizer based receiver with adaptive calibration for chip-to-chip interface

Abstract

A bit error rate (BER) optimum adaptive analog to digital converter (ADC) and equalizer based receiver is presented to reduce ADC resolution for chip-to-chip interface. The proposed receiver compensates for channel dispersion and calibrates reference levels of flash ADC based on digital information in filter. The separated two flash ADCs work as time interleaved 2x oversampling system and feed forward equalizer (FFE) and decision feedback equalizer (DFE) deal with calibration based on least mean square (LMS) algo-rithm. The system performance demonstrations for various resolutions and phases dependency are confirmed with various signal to noise (SNR) conditions. As a result, the proposed system achieves effective resolutions for chip-to-chip interface and reduction of hardware complexity compared with conventional DFE based receivers.