Showing results 1 to 4 of 4
0.1 μm p-channel MOSFETs with 51 GHz fT5 Ω Jeon, Duk Young; Lee, KF; Yan, RH; Kim, YO; Tennant, DM; Westerwick, EH; Chin, GM; et al, Technical Digest of 1992 IEDM Meeting, pp.1012 - 1014, 1992 |
A Half-Microon Super Self-Aligned BiCMOS Technology for High Spped Application Jeon, Duk Young; Liu, TM; Chin, GM; Morris, MD; Archer, VD; Kim, HH; Cerullo, M; et al, Technical Digest of 1992 IEDM Meeting, pp.23 - 26, 1992 |
An Uitra High Spped ECL-Bipolar CMOS Technology with Silicon Fillet Self-aligned Contacts Jeon, Duk Young; Liu, TM; Chin, GM; Morris, MD; Archer, VD; Kim, HH; Cerullo, M; et al, Digest of Technical Papers of 1992 Symposium on VLSI Technilogy, pp.30 - 31, 1992 |
Room Temperature 0.1 um CMOS Technology with 11.8 ps Gate Delay Jeon, Duk Young; Lee, KF; Yan, RH; Chin, GM; Kim, YO; Tennant, DM; Razavi, B; et al, Technical Digest of IEDM 1993, pp.131 - 134, 1993 |
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