DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, K. -I. | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.contributor.author | Park, K. -I. | ko |
dc.contributor.author | Jun, Y. -H. | ko |
dc.contributor.author | Kim, K. | ko |
dc.date.accessioned | 2013-08-14T01:35:40Z | - |
dc.date.available | 2013-08-14T01:35:40Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-09 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.44, no.19, pp.1121 - 1122 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/175092 | - |
dc.description.abstract | A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mu m CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.subject | DELAY-LOCKED LOOP | - |
dc.title | Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface | - |
dc.type | Article | - |
dc.identifier.wosid | 000259155000013 | - |
dc.identifier.scopusid | 2-s2.0-51549106103 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.issue | 19 | - |
dc.citation.beginningpage | 1121 | - |
dc.citation.endingpage | 1122 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el:20081833 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Park, K. -I. | - |
dc.contributor.nonIdAuthor | Jun, Y. -H. | - |
dc.contributor.nonIdAuthor | Kim, K. | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | DELAY-LOCKED LOOP | - |
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