A new wafer level TSV build-up stacking using oxide bonding

Abstract

A new through-silicon via (TSV) build-up stacking method using oxide bonding is proposed and implemented in this work. The proposed method can be applied to the fabrication of a TSV stack chip. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip. Experiments were conducted by oxide bonding of chips and the oxide bonding energy was acquired by a four point bending test. The obtained bonding energy sufficiently exceeds the energy criteria of 3D stacking. Thus, two oxide wafers with an 8 inch diameter were bonded by oxide bonding at the wafer level. The 0.6 mu m thick oxide layers were located between bonded wafers and the top wafer was thinned down to fabricate blind via at the top of bonded wafer. The thickness of the top and bottom wafer is to 70 and 725 mu m, respectively, after the top chemical mechanical polishing (CMP) process. Then blind vias were fabricated by deep reactive ion etching; the diameter and depth of the via is 20 mu m and 150 mu m, respectively. A through hole was formed by bottom CMP; total thickness of the oxide bonded wafer is 140 mu m. The dielectric layer (SiO2), adhesion and diffusion barrier (TiN, Ti) and wetting layer (Cu) were deposited sequentially to improve the wettability of the via wall. Since the molten solder cannot be filled in the via if there is no wetting layer at the via wall. Finally, the vias were successfully filled with molten solder within 10 s.