A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

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dc.contributor.authorDuarte, Juan Pabloko
dc.contributor.authorChoi, Sung-Jinko
dc.contributor.authorMoon, Dong-Ilko
dc.contributor.authorAhn, Jae-Hyukko
dc.contributor.authorKim, Jee-Yeonko
dc.contributor.authorKim, Sung-Hoko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2013-06-07T08:03:13Z-
dc.date.available2013-06-07T08:03:13Z-
dc.date.created2013-05-07-
dc.date.created2013-05-07-
dc.date.issued2013-02-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.2, pp.848 - 855-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/173827-
dc.description.abstractA universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectCOMPACT MODEL-
dc.subjectSOI MOSFETS-
dc.subjectCHANNEL-
dc.titleA Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model-
dc.typeArticle-
dc.identifier.wosid000316817900046-
dc.identifier.scopusid2-s2.0-84872845173-
dc.type.rimsART-
dc.citation.volume60-
dc.citation.issue2-
dc.citation.beginningpage848-
dc.citation.endingpage855-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2012.2233863-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorDuarte, Juan Pablo-
dc.contributor.nonIdAuthorMoon, Dong-Il-
dc.contributor.nonIdAuthorKim, Jee-Yeon-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCompact modeling-
dc.subject.keywordAuthorcylindrical gate-all-around (Cy-GAA) field-effect transistor (FET)-
dc.subject.keywordAuthordouble-gate (DG) FET-
dc.subject.keywordAuthorFinFET-
dc.subject.keywordAuthormultiple-gate FET (Mug-FET)-
dc.subject.keywordAuthorPao-Sah&apos-
dc.subject.keywordAuthors integral-
dc.subject.keywordAuthorPoisson&apos-
dc.subject.keywordAuthors equation-
dc.subject.keywordAuthorrectangular gate-all-around (Re-GAA) FET-
dc.subject.keywordAuthorsemiconductor device modeling-
dc.subject.keywordAuthorsingle-gate (SG) FET-
dc.subject.keywordAuthortriple-gate (TG) FET-
dc.subject.keywordPlusCOMPACT MODEL-
dc.subject.keywordPlusSOI MOSFETS-
dc.subject.keywordPlusCHANNEL-
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