DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hong-Yun | ko |
dc.contributor.author | Kim, Young-Jun | ko |
dc.contributor.author | Oh, Jie-Hwan | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-06-07T07:55:34Z | - |
dc.date.available | 2013-06-07T07:55:34Z | - |
dc.date.created | 2012-06-18 | - |
dc.date.created | 2012-06-18 | - |
dc.date.issued | 2013-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.4, pp.938 - 950 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/173778 | - |
dc.description.abstract | In this paper, we present a reconfigurable SIMT multi-core processor with a shared memory for mobile ray tracing. The proposed processor addresses two issues of SIMT architecture: branch divergence of concurrently executed threads and contention in a shared memory. Performance degradation due to the branch divergence is reduced by dividing a wide SIMT datapath into several narrow SIMT cores that execute independent threads asynchronously. The contention in a shared memory caused by the multiple SIMT cores is alleviated by introducing a new time-division multiplexing (TDM) scheme using multi-phase clocks. The SIMT cores send their requests to a shared memory sequentially not concurrently by synchronizing the SIMT cores with multi-phase clocks to hide arbitration delays. The processor achieves the same datapath utilization as 4-wide SIMT which has been widely used by CPU-based ray tracers while its area remains 68% of the 4-wide SIMT. As a result, the performance normalized to area is improved by 26% compared to previous work with negligible overheads (2.6% for area and 1% for power consumption). The chip was fabricated in 90 nm CMOS technology, and it contains 2.3 M logic gates and 19.3 KB SRAM. It consumes 221 mW at 100 MHz with Vdd = 1.2V. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SYSTEM | - |
dc.title | A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory | - |
dc.type | Article | - |
dc.identifier.wosid | 000317005400012 | - |
dc.identifier.scopusid | 2-s2.0-84875713228 | - |
dc.type.rims | ART | - |
dc.citation.volume | 60 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 938 | - |
dc.citation.endingpage | 950 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2012.2209302 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Kim, Young-Jun | - |
dc.contributor.nonIdAuthor | Oh, Jie-Hwan | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Branch divergence | - |
dc.subject.keywordAuthor | mobile multi-core processor | - |
dc.subject.keywordAuthor | ray tracing | - |
dc.subject.keywordAuthor | shared memory contention | - |
dc.subject.keywordAuthor | SIMT | - |
dc.subject.keywordAuthor | 3-D graphics | - |
dc.subject.keywordPlus | SYSTEM | - |
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