DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Byungchun | ko |
dc.contributor.author | Marcello, Sandra | ko |
dc.contributor.author | Mirbaha, Amir Pasha | ko |
dc.contributor.author | Naccache, David | ko |
dc.contributor.author | Sabeg, Karim | ko |
dc.date.accessioned | 2013-04-29 | - |
dc.date.available | 2013-04-29 | - |
dc.date.created | 2013-04-01 | - |
dc.date.created | 2013-04-01 | - |
dc.date.issued | 2012 | - |
dc.identifier.citation | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v.6805 LNCS, no.0, pp.319 - 328 | - |
dc.identifier.issn | 0302-9743 | - |
dc.identifier.uri | http://hdl.handle.net/10203/173606 | - |
dc.description.abstract | This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both compact and fast. When the operands' bit-length m is 1024, the new algorithm requires only 0.194m + 56 additions (on average), this is about half the number of additions required by the classical accumulate-and-add multiplication algorithm (m/2). © 2012 Springer-Verlag Berlin Heidelberg. | - |
dc.language | English | - |
dc.publisher | Springer Verlag | - |
dc.title | Operand folding hardware multipliers | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-84857723927 | - |
dc.type.rims | ART | - |
dc.citation.volume | 6805 LNCS | - |
dc.citation.issue | 0 | - |
dc.citation.beginningpage | 319 | - |
dc.citation.endingpage | 328 | - |
dc.citation.publicationname | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | - |
dc.contributor.nonIdAuthor | Marcello, Sandra | - |
dc.contributor.nonIdAuthor | Mirbaha, Amir Pasha | - |
dc.contributor.nonIdAuthor | Naccache, David | - |
dc.contributor.nonIdAuthor | Sabeg, Karim | - |
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