mu*-Tree: An Ordered Index Structure for NAND Flash Memory with Adaptive Page Layout Scheme

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dc.contributor.authorAhn, Jung-Sangko
dc.contributor.authorKang, Dong-Wonko
dc.contributor.authorJung, Da-Woonko
dc.contributor.authorKim, Jin-Sooko
dc.contributor.authorMaeng, Seung-Ryoulko
dc.date.accessioned2013-04-11T07:49:07Z-
dc.date.available2013-04-11T07:49:07Z-
dc.date.created2013-04-09-
dc.date.created2013-04-09-
dc.date.issued2013-04-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTERS, v.62, no.4, pp.784 - 797-
dc.identifier.issn0018-9340-
dc.identifier.urihttp://hdl.handle.net/10203/173429-
dc.description.abstractAs NAND flash memory is gaining popularity as a storage medium for mobile embedded devices, many flash-aware file systems, flash-aware DBMSes, and flash translation layers (FTLs) require an flash-efficient index structure. This paper proposes a novel index structure called mu*-Tree which natively works on NAND flash memory, aiming at improving performance over B+-Tree. mu*-Tree stores all the nodes along the path from the root to the leaf into a single flash memory page in order to minimize the number of flash write operation when a node is updated. Furthermore, mu*-Tree has an adaptive page layout scheme which dynamically adjusts the page layout according to the workload characteristics on-the-fly. mu*-Tree also allows flash pages with different page layouts to coexist in the same tree. Our evaluation results with real workload traces show that mu*-Tree outperforms B+-Tree by up to 55 percent in terms of the time needed for flash operations. With a small in-memory cache of 32 KB, mu*-Tree improves the overall performance by up to five times compared to B+-Tree with the same cache size.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.titlemu*-Tree: An Ordered Index Structure for NAND Flash Memory with Adaptive Page Layout Scheme-
dc.typeArticle-
dc.identifier.wosid000315959200012-
dc.identifier.scopusid2-s2.0-84874998707-
dc.type.rimsART-
dc.citation.volume62-
dc.citation.issue4-
dc.citation.beginningpage784-
dc.citation.endingpage797-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTERS-
dc.identifier.doi10.1109/TC.2012.20-
dc.contributor.localauthorMaeng, Seung-Ryoul-
dc.contributor.nonIdAuthorAhn, Jung-Sang-
dc.contributor.nonIdAuthorKang, Dong-Won-
dc.contributor.nonIdAuthorJung, Da-Woon-
dc.contributor.nonIdAuthorKim, Jin-Soo-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorNAND flash memory-
dc.subject.keywordAuthorindex structure-
dc.subject.keywordAuthorB+-Tree-
dc.subject.keywordPlusB-TREE-
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