FEC-based 4 Gb/s Backplane Transceiver in 90nm CMOS

Abstract

This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45 x reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER < 10-12, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.