Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yun, W. | ko |
| dc.contributor.author | Kang, K. | ko |
| dc.contributor.author | Kyung, Chong-Min | ko |
| dc.date.accessioned | 2013-03-28T11:06:17Z | - |
| dc.date.available | 2013-03-28T11:06:17Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2011-05-15 | - |
| dc.identifier.citation | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1672 - 1675 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/165128 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000297265301221 | - |
| dc.identifier.scopusid | 2-s2.0-79960875518 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 1672 | - |
| dc.citation.endingpage | 1675 | - |
| dc.citation.publicationname | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 | - |
| dc.identifier.conferencecountry | BL | - |
| dc.identifier.conferencelocation | Rio de Janeiro | - |
| dc.contributor.localauthor | Kyung, Chong-Min | - |
| dc.contributor.nonIdAuthor | Yun, W. | - |
| dc.contributor.nonIdAuthor | Kang, K. | - |
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