Synthesis of wafer scale graphene layer for future electronic devices

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Publisher
IEICE
Issue Date
2010-07-01
Language
ENG
Citation

2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp.65 - 67

URI
http://hdl.handle.net/10203/165078
Appears in Collection
EE-Conference Papers(학술회의논문)
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