A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Seok-Hee | - |
| dc.date.accessioned | 2013-03-27T03:36:39Z | - |
| dc.date.available | 2013-03-27T03:36:39Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2009-12-09 | - |
| dc.identifier.citation | International Electron Devices Meeting, v., no., pp.647 - 650 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/158707 | - |
| dc.language | ENG | - |
| dc.title | A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 647 | - |
| dc.citation.endingpage | 650 | - |
| dc.citation.publicationname | International Electron Devices Meeting | - |
| dc.identifier.conferencecountry | United States | - |
| dc.identifier.conferencecountry | United States | - |
| dc.contributor.localauthor | Lee, Seok-Hee | - |
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