Register allocation for high-level synthesis using dual supply voltages

Abstract

Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-V-dd. Specifically, we propose a complete design framework that starts from dual-V-dd scheduling, dual-V-dd allocation, and controller synthesis down to the final layout. Its main feature is dual-V-dd register allocation, which exploits timing slacks left in the data-path after operation scheduling. In experiments on benchmark designs implemented in 1.08 V (with V-ddl of 0.8 V), 65-nm CMOS technology, both switching and leakage power were reduced by 20% on average, respectively, compared to data-path with dual-V-dd applied to functional units alone. Detailed analysis of slack histogram, area, wirelength, and congestion were performed to assess feasibility of the design framework.