A Delay Line Circuit Layout For Crosstalk Minimization Using Genetic Algorithm and Experimental Verification
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Joungho | - |
| dc.contributor.author | Chung, Chaeho | - |
| dc.contributor.author | Lee, Soobum | - |
| dc.contributor.author | Kwak, Byungman | - |
| dc.contributor.author | Kim, Gawon | - |
| dc.date.accessioned | 2013-03-19T04:12:37Z | - |
| dc.date.available | 2013-03-19T04:12:37Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2007 | - |
| dc.identifier.citation | World Congress on Structural and Multidisciplinary Optimization, v., no., pp. - | - |
| dc.identifier.uri | http://hdl.handle.net/10203/155569 | - |
| dc.language | ENG | - |
| dc.title | A Delay Line Circuit Layout For Crosstalk Minimization Using Genetic Algorithm and Experimental Verification | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | World Congress on Structural and Multidisciplinary Optimization | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.contributor.localauthor | Kim, Joungho | - |
| dc.contributor.nonIdAuthor | Chung, Chaeho | - |
| dc.contributor.nonIdAuthor | Lee, Soobum | - |
| dc.contributor.nonIdAuthor | Kwak, Byungman | - |
| dc.contributor.nonIdAuthor | Kim, Gawon | - |
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.