Minimizing leakage power in sequential circuits by using mixed Vt flip-flops

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dc.contributor.authorKim, J.-
dc.contributor.authorShin, Youngsoo-
dc.date.accessioned2013-03-19T00:31:52Z-
dc.date.available2013-03-19T00:31:52Z-
dc.date.created2012-02-06-
dc.date.issued2007-11-04-
dc.identifier.citation2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, v., no., pp.797 - 802-
dc.identifier.issn1092-3152-
dc.identifier.urihttp://hdl.handle.net/10203/154058-
dc.languageENG-
dc.titleMinimizing leakage power in sequential circuits by using mixed Vt flip-flops-
dc.typeConference-
dc.identifier.scopusid2-s2.0-50249095755-
dc.type.rimsCONF-
dc.citation.beginningpage797-
dc.citation.endingpage802-
dc.citation.publicationname2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorShin, Youngsoo-
dc.contributor.nonIdAuthorKim, J.-
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EE-Conference Papers(학술회의논문)
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