Xilinx GTP 인터페이스와 DDR-2 메모리를 이용한 고속 데이터 처리 유닛 개발에 관한 연구High Speed Data Processing Unit Development Using Xilinx GTP Interface and DDR-2 Memory

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 1029
  • Download : 337
This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.
Publisher
한국항공우주학회
Issue Date
2008-08
Language
Korean
Citation

한국항공우주학회지, v.36, no.8, pp.816 - 823

ISSN
1225-1348
URI
http://hdl.handle.net/10203/15222
Appears in Collection
AE-Journal Papers(저널논문)
Files in This Item

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0