Formal Verification Method for Nuclear I&C Systems using ESDT and SMV in the Software Design Phase

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dc.contributor.authorSong, Myung Jun-
dc.contributor.authorKoo, Seo Ryong-
dc.contributor.authorSeong, Poong-Hyun-
dc.date.accessioned2013-03-18T14:54:32Z-
dc.date.available2013-03-18T14:54:32Z-
dc.date.created2012-02-06-
dc.date.issued2004-10-
dc.identifier.citationNUTHOS-6, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/149461-
dc.languageENG-
dc.titleFormal Verification Method for Nuclear I&C Systems using ESDT and SMV in the Software Design Phase-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnameNUTHOS-6-
dc.identifier.conferencecountryJapan-
dc.identifier.conferencecountryJapan-
dc.contributor.localauthorSeong, Poong-Hyun-
dc.contributor.nonIdAuthorSong, Myung Jun-
dc.contributor.nonIdAuthorKoo, Seo Ryong-
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NE-Conference Papers(학술회의논문)
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