An efficient block-matching criterion for motion estimation and its VLSI implementation

Abstract

The block-matching motion estimation is the most popular technique for motion compensated coding of image sequence. Due to the intensive computational requirement to perform motion estimation(ME) in real-time, application specific VLSI implementation of the ME is indispensable. In this paper, we present a novel block-matching criterion for motion estimation called Reduced Bits Mean Absolute Difference(RBMAD). By comparison with conventional schemes, our scheme reduces hardware requirement and increases the speed of computation in VLSI chip with acceptable video performance. We describe in details the video performances of proposed criterion and conventional ones. We also show our VLSI implementation using the proposed scheme to compare the hardware requirement and operating speed with conventional ones. It is found that RBMAD using 4bits has reasonable video performance with 57% less VLSI area and 34% faster, thus it is suitable for low cost applications of video coding.