Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator
- Issue Date
- 2005-10-24
- Language
- ENG
- Citation
ASICON 2005: 2005 6th International Conference on ASIC, v.1, pp.140 - 143
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
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