Leakage power minimization for the synthesis of parallel multiplier circuits

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dc.contributor.authorShin K.-
dc.contributor.authorKim T.-
dc.date.accessioned2013-03-17T04:23:41Z-
dc.date.available2013-03-17T04:23:41Z-
dc.date.created2012-02-06-
dc.date.issued2004-04-26-
dc.identifier.citationProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, v., no., pp.166 - 169-
dc.identifier.urihttp://hdl.handle.net/10203/139802-
dc.languageENG-
dc.titleLeakage power minimization for the synthesis of parallel multiplier circuits-
dc.typeConference-
dc.identifier.scopusid2-s2.0-2942654737-
dc.type.rimsCONF-
dc.citation.beginningpage166-
dc.citation.endingpage169-
dc.citation.publicationnameProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorShin K.-
dc.contributor.nonIdAuthorKim T.-
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