Leakage power minimization for the synthesis of parallel multiplier circuits
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Shin K. | - |
| dc.contributor.author | Kim T. | - |
| dc.date.accessioned | 2013-03-17T04:23:41Z | - |
| dc.date.available | 2013-03-17T04:23:41Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2004-04-26 | - |
| dc.identifier.citation | Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, v., no., pp.166 - 169 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/139802 | - |
| dc.language | ENG | - |
| dc.title | Leakage power minimization for the synthesis of parallel multiplier circuits | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-2942654737 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 166 | - |
| dc.citation.endingpage | 169 | - |
| dc.citation.publicationname | Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era | - |
| dc.identifier.conferencecountry | United States | - |
| dc.identifier.conferencecountry | United States | - |
| dc.contributor.localauthor | Shin K. | - |
| dc.contributor.nonIdAuthor | Kim T. | - |
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