A pipelined VLSI architecture for a list sphere decoder
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee J. | - |
| dc.contributor.author | Park, Sin Chong | - |
| dc.contributor.author | Park S. | - |
| dc.date.accessioned | 2013-03-17T02:04:52Z | - |
| dc.date.available | 2013-03-17T02:04:52Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2006-05-21 | - |
| dc.identifier.citation | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, v., no., pp.397 - 400 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/138652 | - |
| dc.language | ENG | - |
| dc.title | A pipelined VLSI architecture for a list sphere decoder | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-34547291178 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 397 | - |
| dc.citation.endingpage | 400 | - |
| dc.citation.publicationname | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems | - |
| dc.identifier.conferencecountry | Greece | - |
| dc.identifier.conferencecountry | Greece | - |
| dc.contributor.localauthor | Park, Sin Chong | - |
| dc.contributor.nonIdAuthor | Lee J. | - |
| dc.contributor.nonIdAuthor | Park S. | - |
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