Heurisic Algorithm for Minimizing Earliness-Tardiness on a Single Burn-in Oven in Semiconductor Manufacturing. Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing

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Issue Date
2002
Language
ENG
Citation

International Conference on Modeling and Analysis of Semiconductor Manufacturing, pp.217 - 222

URI
http://hdl.handle.net/10203/136036
Appears in Collection
IE-Conference Papers(학술회의논문)
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