Heurisic Algorithm for Minimizing Earliness-Tardiness on a Single Burn-in Oven in Semiconductor Manufacturing. Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing
- Issue Date
- 2002
- Language
- ENG
- Citation
International Conference on Modeling and Analysis of Semiconductor Manufacturing, pp.217 - 222
- Appears in Collection
- IE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
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