Loop and Address Code Optimization for Digital Signal Processors
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, JY | - |
| dc.contributor.author | Park, In-Cheol | - |
| dc.date.accessioned | 2013-03-16T19:47:11Z | - |
| dc.date.available | 2013-03-16T19:47:11Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2002-02 | - |
| dc.identifier.citation | 한국반도체학술대회 (KCS), v., no., pp.103 - 104 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/135122 | - |
| dc.language | KOR | - |
| dc.title | Loop and Address Code Optimization for Digital Signal Processors | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 103 | - |
| dc.citation.endingpage | 104 | - |
| dc.citation.publicationname | 한국반도체학술대회 (KCS) | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.contributor.localauthor | Park, In-Cheol | - |
| dc.contributor.nonIdAuthor | Lee, JY | - |
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