A VLSI Architecture for Blind Decision Feedback Equalizer

Abstract

This paper presents a VLSI architecture and implementation of a blind decision feedback equalizer for cable modem. The presented Decision Feedback Equalizer accommodates 64- and 256-QAM formats, and incorporates an adaptive feedforward equalizer (FFE), an adaptive decision feedback equalizer (DFE), a carry recovery loop, and a error monitor. The FFE and DFE are both 16-tap filters based on a signed-LMS coefficient updating algorithm. The FFE is a T/2-spaced fractional equalizer, The maximum clock rate of the chip is projected to be 50 MHz, for which the equalizer operates at 6 Mbaud maximum symbol rate, The equalizer is to be fabricated in 0.35-micron CMOS, and requires an estimated 100,000 gates.