Test Pattern Generation of Combinational Circuits using Logic Decision Diagrams
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lim, Jong-Tae | - |
| dc.contributor.author | Lee, MS | - |
| dc.date.accessioned | 2013-03-16T09:47:59Z | - |
| dc.date.available | 2013-03-16T09:47:59Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2000-10 | - |
| dc.identifier.citation | ISIM 2000, v., no., pp.375 - 378 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/130024 | - |
| dc.language | ENG | - |
| dc.title | Test Pattern Generation of Combinational Circuits using Logic Decision Diagrams | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 375 | - |
| dc.citation.endingpage | 378 | - |
| dc.citation.publicationname | ISIM 2000 | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.contributor.localauthor | Lim, Jong-Tae | - |
| dc.contributor.nonIdAuthor | Lee, MS | - |
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