A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, S.-J. | ko |
| dc.contributor.author | Kim, J.-S. | ko |
| dc.contributor.author | Woo, R. | ko |
| dc.contributor.author | Lee, S.-J. | ko |
| dc.contributor.author | Lee, K.-M. | ko |
| dc.contributor.author | Yang, T.-H. | ko |
| dc.contributor.author | Jung, J.-Y. | ko |
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.date.accessioned | 2013-03-16T04:27:34Z | - |
| dc.date.available | 2013-03-16T04:27:34Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2001-06-14 | - |
| dc.identifier.citation | 2001 VLSI Circuits Symposium, pp.233 - 236 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/127452 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000173132600075 | - |
| dc.identifier.scopusid | 2-s2.0-0034794941 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 233 | - |
| dc.citation.endingpage | 236 | - |
| dc.citation.publicationname | 2001 VLSI Circuits Symposium | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Kyoto | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
| dc.contributor.nonIdAuthor | Park, S.-J. | - |
| dc.contributor.nonIdAuthor | Kim, J.-S. | - |
| dc.contributor.nonIdAuthor | Woo, R. | - |
| dc.contributor.nonIdAuthor | Lee, S.-J. | - |
| dc.contributor.nonIdAuthor | Lee, K.-M. | - |
| dc.contributor.nonIdAuthor | Yang, T.-H. | - |
| dc.contributor.nonIdAuthor | Jung, J.-Y. | - |
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