Dual-Loop Digital PLL Design for Adaptive Clock Recovery
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Beom-Sup Kim | ko |
| dc.date.accessioned | 2013-03-15T14:18:07Z | - |
| dc.date.available | 2013-03-15T14:18:07Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1998-02 | - |
| dc.identifier.citation | ASP-DAC'98, pp.347 - 352 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/120171 | - |
| dc.language | English | - |
| dc.publisher | ASP-DAC | - |
| dc.title | Dual-Loop Digital PLL Design for Adaptive Clock Recovery | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000073939900063 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 347 | - |
| dc.citation.endingpage | 352 | - |
| dc.citation.publicationname | ASP-DAC'98 | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Yokohama | - |
| dc.contributor.localauthor | Beom-Sup Kim | - |
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