Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolationDouble spacer LOCOS process with shallow recess of silicon for 0.20 um isolation
- Issue Date
- 1996-08-26
- Language
- ENG
- Citation
International Conf. on Solid State Devices and Materials (SSDM), pp.40 - 40
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.