DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Kyu Ho | - |
dc.contributor.author | Chung, S.W. | - |
dc.contributor.author | Hong, K.P. | - |
dc.date.accessioned | 2013-03-14T22:23:07Z | - |
dc.date.available | 2013-03-14T22:23:07Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1986 | - |
dc.identifier.citation | KIEE, v., no., pp. - | - |
dc.identifier.uri | http://hdl.handle.net/10203/113972 | - |
dc.language | KOR | - |
dc.title | Verification and Diagnosis of Logic Design using Temporal Logic | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | KIEE | - |
dc.identifier.conferencecountry | South Korea | - |
dc.identifier.conferencecountry | South Korea | - |
dc.contributor.localauthor | Park, Kyu Ho | - |
dc.contributor.nonIdAuthor | Chung, S.W. | - |
dc.contributor.nonIdAuthor | Hong, K.P. | - |
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