DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, SH | ko |
dc.contributor.author | Yoon, JS | ko |
dc.contributor.author | Yu, CH | ko |
dc.contributor.author | Kim, D | ko |
dc.contributor.author | Chung, K | ko |
dc.contributor.author | Lim, HS | ko |
dc.contributor.author | Lee, YG | ko |
dc.contributor.author | Park, HyunWook | ko |
dc.contributor.author | Ra, Jong Beom | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2009-09-09T05:49:38Z | - |
dc.date.available | 2009-09-09T05:49:38Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-05 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.43, pp.1247 - 1259 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/11107 | - |
dc.description.abstract | In this paper, a 3-D display processor embedding a programmable 3-D graphics rendering engine is proposed. The proposed processor combines a 3-D graphics rendering engine and a 3-D image synthesis engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3-D graphics data and 3-D display inputs, both pipelines are merged by sharing buffers such that a 3-D display engine directly uses the output of a 3-D graphics rendering engine. The merged architecture has synergetic coupling effects such as freely providing various rendering effects to 3-D images and easily computing disparities without complex extraction processes. In the 3-D image synthesis engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3-D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3-D graphics rendering engine is programmable and supports the instruction sets of the latest 3-D graphics standard APIs, Pixel Shader 3.0 and OpenGL|ES 2.0. The die contains about 1.7M transistors, occupies 5 mm x 5 mm in 0.18 mu m CMOS and dissipates 379 mW at 1.85 V. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 36 fps SXGA 3-D display processor embedding a programmable 3-D graphics rendering engine | - |
dc.type | Article | - |
dc.identifier.wosid | 000255354300020 | - |
dc.identifier.scopusid | 2-s2.0-42649117171 | - |
dc.type.rims | ART | - |
dc.citation.volume | 43 | - |
dc.citation.beginningpage | 1247 | - |
dc.citation.endingpage | 1259 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2008.920315 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, HyunWook | - |
dc.contributor.localauthor | Ra, Jong Beom | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | multiplexing | - |
dc.subject.keywordAuthor | pixel shader | - |
dc.subject.keywordAuthor | three-dimensional displays | - |
dc.subject.keywordAuthor | three-dimensional graphics | - |
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