Pipelined systolic arrays architecture for the hierarchical block-matching algorithm

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Publisher
IEEE
Issue Date
1994-05-30
Language
ENG
Citation

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.3, pp.221 - 224

ISSN
0271-4310
URI
http://hdl.handle.net/10203/108012
Appears in Collection
CS-Conference Papers(학술회의논문)
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