Efficient Wafer-Level Edge-Tracing Technique for 3-D Interconnection of Stacked Die

Abstract

An efficient edge-tracing technique at the wafer-level is proposed and implemented in this paper. The proposed method can be applied to the fabrication of a stacked chip. Experiments were conducted by stacking four test chips each 100-mu m-thick, and the configuration of the pad is based on a memory chip from an electronics company. The chips for stacking were fabricated by half-dicing the wafer and curing the adhesives in a trench. When the four chips were built up and metallized, the stacked chip was 430-mu m high, which is comparable to that of a through-silicon via. The daisy chain resistance of the interconnection was measured to be 5 Omega, and further improvement is possible with modification. The interconnection quality of the stacked chip was examined through 3-D images obtained via computed tomography and X-ray imageries. The images proved the successful creation of the interconnections. The mechanical integrity of the stacked package meets the 85 degrees C/85% relative humidity test, and the thermal stress analysis is implemented to investigate the reliability issues at the edge of the chip, and it is concluded that there are no critical reliability problems.