DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Ki-Yeong | ko |
dc.contributor.author | Hwang, Chul-Soon | ko |
dc.contributor.author | Koo, Kyoung-Choul | ko |
dc.contributor.author | Cho, Jong-Hyun | ko |
dc.contributor.author | Kim, Hee-Gon | ko |
dc.contributor.author | Kim, Joung-Ho | ko |
dc.contributor.author | Lee, Jun-Ho | ko |
dc.contributor.author | Lee, Hyung-Dong | ko |
dc.contributor.author | Park, Kun-Woo | ko |
dc.contributor.author | Pak, Jun-So | ko |
dc.date.accessioned | 2013-03-12T16:19:28Z | - |
dc.date.available | 2013-03-12T16:19:28Z | - |
dc.date.created | 2012-07-06 | - |
dc.date.created | 2012-07-06 | - |
dc.date.issued | 2012-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.2, no.12, pp.2057 - 2070 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.uri | http://hdl.handle.net/10203/102848 | - |
dc.description.abstract | In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SEGMENTATION | - |
dc.subject | PACKAGE | - |
dc.subject | DESIGN | - |
dc.title | Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects | - |
dc.type | Article | - |
dc.identifier.wosid | 000312459800015 | - |
dc.identifier.scopusid | 2-s2.0-84871057946 | - |
dc.type.rims | ART | - |
dc.citation.volume | 2 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 2057 | - |
dc.citation.endingpage | 2070 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.identifier.doi | 10.1109/TCPMT.2012.2214482 | - |
dc.contributor.localauthor | Kim, Joung-Ho | - |
dc.contributor.nonIdAuthor | Lee, Hyung-Dong | - |
dc.contributor.nonIdAuthor | Park, Kun-Woo | - |
dc.contributor.nonIdAuthor | Pak, Jun-So | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 3-D stacked on-chip power distribution network (PDN) | - |
dc.subject.keywordAuthor | on-chip decoupling capacitor (decap) | - |
dc.subject.keywordAuthor | on-chip PDN | - |
dc.subject.keywordAuthor | PDN impedance | - |
dc.subject.keywordAuthor | power/ground (P/G) TSV | - |
dc.subject.keywordAuthor | silicon substrate | - |
dc.subject.keywordAuthor | through silicon via (TSV)-based 3-D ICs | - |
dc.subject.keywordPlus | SEGMENTATION | - |
dc.subject.keywordPlus | PACKAGE | - |
dc.subject.keywordPlus | DESIGN | - |
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