Offset-tolerant design of analog chips for independent component analysis

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dc.contributor.authorCho, KSko
dc.contributor.authorLee, Soo-Youngko
dc.date.accessioned2009-07-23T02:52:36Z-
dc.date.available2009-07-23T02:52:36Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2004-08-
dc.identifier.citationIEICE TRANSACTIONS ON ELECTRONICS, v.E87C, pp.1382 - 1387-
dc.identifier.issn0916-8524-
dc.identifier.urihttp://hdl.handle.net/10203/10219-
dc.description.abstractAn analog neurochip for independent component analysis (ICA) is designed with on-line learning capability. Due to the limited dynamic range of analog device, the nonholonomic ICA algorithm is adopted. In order to accommodate the offsets due to device mismatches, a modified algorithm is developed with 2-quadrant multipliers and self-adjusting biases. Performance of the developed system was demonstrated by Monte-Carlo simulation.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.subjectSEPARATION-
dc.titleOffset-tolerant design of analog chips for independent component analysis-
dc.typeArticle-
dc.identifier.wosid000223264700028-
dc.identifier.scopusid2-s2.0-4344561950-
dc.type.rimsART-
dc.citation.volumeE87C-
dc.citation.beginningpage1382-
dc.citation.endingpage1387-
dc.citation.publicationnameIEICE TRANSACTIONS ON ELECTRONICS-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorLee, Soo-Young-
dc.contributor.nonIdAuthorCho, KS-
dc.type.journalArticleLetter-
dc.subject.keywordAuthorneurochip-
dc.subject.keywordAuthoroffset tolerance-
dc.subject.keywordAuthorICA-
dc.subject.keywordAuthorblind signal separation-
dc.subject.keywordPlusSEPARATION-
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