Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays

Abstract

This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 mu m standard CMOS process for a 150 x 64 CdTe X-ray detector array. The readout circuit was found to effectively increase the charge storage capacity up to 1.6 x 10(8) electrons, providing an improved SNR by a factor of approximately 8. The measured equivalent noise charge resulting from the readout circuit was 1.68 x 10(4) electrons, a negligible value compared to the shot noise from the detector.