High gain and high efficiency CMOS power amplifier using multiple design techniques

Abstract

A 60 GHz power amplifier (PA) using standard 90 nm CMOS technology is presented. This PA has power gain greater than 30 dB and 18.3% peak power added efficiency (PAE) under 2 V supply voltage. The parallel arrayed cascode power cells, which have a small number of fingers, are combined by the delay line to produce high gain and high PAE. Common gate inductors are inserted as gain booster circuits. A diode lineariser (DL) is adopted for increasing PAE and output P1dB (OP1dB). The measured saturation power is 13.2 dBm with its 11.5 dBm OP1dB. The measure power gain is above 25 dB over the whole frequency range (56-65 GHz). Due to the DL, the measured PAE exceeds 14% at the OP1dB power. This is believed to be the first CMOS PA having such high power gain and PAE.