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Showing results 1 to 7 of 7

1
A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks

Li, Youjie; PARK, JONGSE; Alian, Mohammad; Yuan, Yifan; Qu, Zheng; Pan, Peitian; Wang, Ren; et al, International Symposium on Microarchitecture (MICRO), IEEE/ACM, 2018-10-24

2
CoVA: Exploiting Compressed-Domain Analysis to Accelerate Video Analytics

Hwang, Jinwoo; Kim, Minsoo; Kim, Daeun; Nam, Seungho; Kim, Yoonsung; Kim, Dohee; Sharma, Hardik; et al, 2022 USENIX Annual Technical Conference, ATC 2022, pp.707 - 721, USENIX (The Advanced Computing Systems Association), 2022-07-12

3
From Tensors to FPGAs: Accelerating Deep Learning

Sharma, Hardik; PARK, JONGSE; Samynathan, Balavinayagam; Robatmili, Behnam; Mirkhani, Shahrzad; Esmaeilzadeh, Hadi, Hot Chips: Symposium on High Performance Chips, IEEE/ACM, 2018-08-19

4
Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic

Ghodrati, Soroush; Sharma, Hardik; Kinzer, Sean; Yazdanbakhsh, Amir; PARK, JONGSE; Kim, Nam Sung; Burger, Doug; et al, International Conference on Parallel Architectures and Compilation Techniques (PACT), ACM SIGARCH,IEEE Computer Society, 2020-10-07

5
Serving Heterogeneous Machine Learning Models on Multi-GPU Servers with Spatio-Temporal Sharing

Choi, Seungbeom; Lee, Sunho; Kim, Yeonjae; PARK, JONGSE; Kwon, Youngjin; Huh, Jaehyuk, 2022 USENIX Annual Technical Conference, USENIX (The Advanced Computing Systems Association), 2022-07-11

6
Supporting Dynamic Translation Granularity for Hybrid Memory Systems

Kim, Bokyeong; Hwang, Soojin; Cha, Sanghoon; Park, Chang Hyun; PARK, JONGSE; Huh, Jaehyuk, The 40th IEEE International Conference on Computer Design, ICCD 2022, pp.25 - 32, IEEE, 2022-10-24

7
Tunable Memory Protection for Secure Neural Processing Units

Lee, Sunho; Na, Seonjin; Kim, Jungwoo; PARK, JONGSE; Huh, Jaehyuk, The 40th IEEE International Conference on Computer Design, ICCD 2022, pp.105 - 108, IEEE, 2022-10-24

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