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A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs Kim, Si-Nai; Kim, Woo Cheol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158, 2018-09 |
Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s Jeon, Yeseul; Kim, Heegon; Kim, Joungho; Je, Minkyu, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.7, pp.2293 - 2303, 2018-07 |
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