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Showing results 1 to 4 of 4

1
40-Gb/s package design using wire-bonded plastic ball grid array

Kam, Dona Gun; Kim, Joungho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.31, no.2, pp.258 - 266, 2008-05

2
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator

Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04

3
Bayesian Exploration Imitation Learning-Based Contextual via Design Optimization Method of PAM-4-Based High-Speed Serial Link

Kim, Jihun; Kim, Minsu; Kim, Haeyeon; Park, Hyunwook; Choi, Seonguk; Park, Joonsang; Sim, Boogyo; et al, IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.65, no.6, pp.1751 - 1762, 2023-12

4
Design of high-performance and low-cost channel in high-speed serial link = 고속 직렬 링크 내 저가형 고성능 채널 설계link

Kam, Dong-Gun; 감동근; et al, 한국과학기술원, 2006

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