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A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.12, pp.3527 - 3537, 2022-12 |
저전력 낮은 기준주파수 스퍼의 시간 저장기를 이용한 2.4GHz 체배지연동기루프 기반의 클럭 생성기 = A low-power and a low-spur 2.4GHz MDLL-based clock generator using time registerlink 김현익; Kim, Hyun Ik; et al, 한국과학기술원, 2015 |
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