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Showing results 1 to 3 of 3

1
A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

Lee, Woo-Jin; Kim, Jae-Min; Ryu, Chung-Hyun; Park, Jong-Bae; Kim, Jun-Chul; Kim, Joung-Ho, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, pp.512 - 514, 2009-08

2
(A) novel low jitter and skew clock distribution network for 3-D stacked chip package = 3차원 적층 칩 패키지를 위한 새로운 저 지터, 저 스큐 클럭 신호 분배 네트워크link

Lee, Woo-Jin; 이우진; et al, 한국과학기술원, 2011

3
Suppression of power/ground inductive impedance and simultaneous switching noise using silicon through-via in a 3-D stacked chip package

Ryu, C; Park, J; Pak, JS; Lee, K; Oh, T; Kim, Joungho, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.17, pp.855 - 857, 2007-12

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