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Showing results 5 to 11 of 11

5
Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training

Han, Wontak; Heo, Jaehoon; Kim, Junsoo; Lim, Sukbin; Kim, Joo-Young, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.12, no.2, pp.354 - 366, 2022-06

6
Design Study and High-power Beam Test of the 60-MeV Linac for Femtosecond THz Radiation at the PAL

Yim, Changmook; Ko, Junho; Ko, In Soo; Jung, Seonghoon; Park, Jaehun; Park, Yong-Jung; Kang, Heung-Sik; et al, JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.59, no.4, pp.2702 - 2708, 2011

7
FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems

Gweon, Surin; Kang, Sanghoon; Kim, Kwantae; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.10, pp.2944 - 2956, 2022-10

8
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching

Han, Donghyeon; Im, Dongseok; Park, Gwangtae; Kim, Youngwoo; Song, Seokchan; Lee, Juhyoung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.9, pp.2858 - 2869, 2021-09

9
Real-Time SSDLite Object Detection on FPGA

Suchang Kim; Na, Seungho; Kong, Byeong Yong; Choi, Jae Woong; Park, In-Cheol, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.6, pp.1192 - 1205, 2021-06

10
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit

Kim, Sangyeob; Kim, Sangjin; Um, Soyeon; Kim, Soyeon; Lee, Juhyoung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.10, pp.2812 - 2825, 2023-10

11
The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices

Lee, Jinsu; Kang, Sanghoon; Lee, Jinmook; Shin, Dongjoo; Han, Donghyeon; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.10, pp.3458 - 3470, 2020-10

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