(A) low noise phase-locked loop design by loop bandwidth optimization

Abstract

This paper describes a low noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-p.m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method. The measured rms and peakto-peak jitter of the PLL at the optimal loop-bandwidth are 3.1ps and 22ps, respectively.