DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Beom-Sup | - |
dc.contributor.advisor | 김범섭 | - |
dc.contributor.author | Lim, Kyoo-Hyun | - |
dc.contributor.author | 임규현 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2002 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174606&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35974 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ [vi], 108, [1] p. ] | - |
dc.description.abstract | This paper describes a low noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-p.m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method. The measured rms and peakto-peak jitter of the PLL at the optimal loop-bandwidth are 3.1ps and 22ps, respectively. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Low Noise | - |
dc.subject | PLL | - |
dc.subject | Loop Bandwidth | - |
dc.subject | 최적화 | - |
dc.subject | 루프대역 | - |
dc.subject | 저잡음 | - |
dc.subject | Optimization | - |
dc.title | (A) low noise phase-locked loop design by loop bandwidth optimization | - |
dc.title.alternative | 루프 대역의 최적화에 의한 저 잡음 PLL 설계 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 174606/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000975318 | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.localauthor | 김범섭 | - |
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