PABC

Abstract

Power consumed by the memory system becomes a serious issue as the size of installed memory increases. With various low power modes that can be applied to each memory unit, the operating system can reduce the number of active memory units by collocating active pages onto a few memory units. This paper presents a memory management scheme based on this observation, which differs from other approaches in that all the memory space is considered while previous ones deal only with pages mapped to user address spaces. The buffer cache usually takes more than half of the total memory, and the pages access patterns are different from those made in user address spaces. Based on an analysis of buffer cache behavior and its interaction with user space our scheme achieves up to 63% more power reduction. Migrating a page to a different memory unit increases memory latencies, but it is shown to reduce additional 4.4% of consumed power.