Plasma doping technology for fabrication of nanoscale metal-oxide-semiconductor devices

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We developed a plasma doping (PLAD) technique which is appropriate for the nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) fabrications. Silicon-on-insulator (SOI) n-MOSFETs with a 50-nm-length metal gate and a 100-nm-channel width were successfully fabricated. The source and drain extensions (SDE) of SOI n-MOSFETs were formed using a plasma doping technique. The advantage of this process is the exclusion of additional activation annealing after introduction of impurity in SDE, which resulted in a laterally abrupt source/drain (S/D) junction profile. We can obtain a low sheet resistance by the PLAD technique and low damaged shallow junctions. A trigate structure SOI n-MOSFET with a gate length of 50 nm fabricated by high-temperature plasma doping revealed suppressed short-channel effects. (C) 2004 American Vacuum Society.
Publisher
American Institute of Physics
Issue Date
2004-11
Language
English
Article Type
Article; Proceedings Paper
Citation

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, v.22, no.6, pp.3210 - 3213

ISSN
1071-1023
DOI
10.1116/1.1813461
URI
http://hdl.handle.net/10203/268220
Appears in Collection
MS-Journal Papers(저널논문)
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