DeepHiR : Improving High-radix Router Throughput with Deep Hybrid Memory Buffer Microarchitecture

Abstract

Hierarchical high-radix router microarchitecture consisting of small SRAM-based intermediate buffers have been used in large-scale supercomputers interconnection networks. While hierarchical organization enables efficient scaling to higher switch port count, it requires intermediate buffers that can cause performance bottleneck. Shallow intermediate buffers can cause head-of-line blocking and result in backpressure towards the input buffers to reduce overall performance. Increasing intermediate buffer size overcomes this problem but is infeasible since the amount of intermediate buffer is proportional to O(p2) where p is the router radix. Adopting new memory technology with higher density can increase intermediate buffer size but is not practical in decentralized, small-size intermediate buffers. In this work, we propose to organise the decentralized intermediate buffers as centralized buffers and leverage alternate memory technology to increase the buffer capacity for high-radix routers. In particular, we exploit Spin-Torque Transfer Magnetic RAM (STT-MRAM) to provide high-density and increase intermediate buffer depths while providing near-zero leakage power. STT-MRAM does result in significant overhead with larger amount of write/read ports that is necessary to support speedup. To overcome this cost, we propose DeepHiR, a novel deep hybrid buffer organization (STT-MRAM and SRAM) combined with a centralized buffer organization to provide high performance with minimal cost.