Timing optimization in SADP process through wire widening and double via insertion

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 316
  • Download : 0
As the minimum feature size continues to shrink down, the interconnect resistance is getting more important. The wire RC delay now often limits the overall chip performance. In this paper, we address a wire width optimization in self-aligned double patterning (SADP) process, where wire widening and double via insertion are considered simultaneously to minimize the total wire delay of timing critical paths. For each of the wires on the critical paths, the candidate directions to which we enlarge the wire is identified while design rules are taken into account. Each candidate direction is then evaluated in terms of the potential wire delay reduction. We finally select an optimal widening configuration by reducing the problem into a minimum weight independent set (MWIS), which is solved by using an integer learning programming (ILP) solver. Experiments are conducted for a few test circuits; wire resistance is reduced by 22.4%, on average, which allows the clock period to be reduced by 12.5%.
Publisher
SPIE
Issue Date
2018-02-28
Language
English
Citation

SPIE Advanced Lithography

DOI
10.1117/12.2297496
URI
http://hdl.handle.net/10203/240188
Appears in Collection
EE-Conference Papers(학술회의논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0